In for the high-speed data signal processing and

In various DSP applications include audio and speech
signal processing, sonar
and radar signal processing, sensor array processing, spectral estimation,
statistical signal processing, digital
image processing, signal
processing for communications, control of systems, biomedical signal
processing, seismic data processing, Filter
designing & many high precision based 
operations. Floating point operations are used due to its great dynamic
range, high precision and easy operation rules. With the increasing
requirements for the floating point operations for the high-speed data signal
processing and the scientific operation, the requirements for the high-speed
hardware floating point arithmetic units have become more and more exigent.

Keywords—
Arithmatic Logic Unit, Digital Signal Prosessing, Floating Point, FPGA,
Multiplier, Super computing, Synergistic Processor, Quadraple Pricision,

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I.         
 Introduction

The implementation of
the floating point arithmetic has been convenient in the floating point high
level languages, but the implementation of the arithmetic by hardware has been
very difficult. With the development of the very large scale integration (VLSI)
technology have become the best options for implementing floating hardware arithmetic
units because of their high integration density, low price, high performance
and flexible applications requirements for high precious operation.

The IEEE 754 standard presents two different floating point formats,
Binary interchange format and Decimal interchange format. This paper focuses
only on single precision normalized binary interchange format. Figure 1 shows
the IEEE 754 single precision binary format representation, it consists of a
one bit sign (S), an eight bit exponent (E), and a twenty three bit fraction
(M) or Mantissa.

   
II.        
Vfloat: A variable precision
fixed- and floatingpoint library for reconfigurable hardware

In this paper, Author presents a variable precision floating-point
library (VFloat) that supports general floating-point formats including IEEE
standard formats. Optimal reconfigurable hardware implementations may require
the use of arbitrary floating-point formats that do not necessarily conform to
IEEE specified sizes. Most previously published floating-point formats for use
with reconfigurable hardware are subsets of our format. Custom datapaths with
optimal bitwidths for each operation can be built using the variable precision
hardware modules in the VFloat library, enabling a higher level of parallelism.

The VFloat library includes three types of hardware modules for
format control, arithmetic operations, and conversions between fixed-point and
floating-point formats. The format conversions allow for hybrid fixed- and
floating-point operations in a single design. This gives the designer control
over a large number of design possibilities including format as well as number
range within the same application. In this article, we give an overview of the
components in the VFloat library and demonstrate their use in an implementation
of the K-means clustering algorithm applied to multispectral satellite images
1.

 

                                                                           
III.       
Fast , Efficient Floting Point
Aders and Multipliers for FPGA

In this article Author presents implementation details for an
IEEE-754 standard floating-point adder and multiplier for FPGAs Floating-point
applications are a growing trend in the FPGA community. As such, it has become
critical to create floating-point units optimized for standard FPGA technology.
Unfortunately, the FPGA design space is very different from the VLSI design
space; thus, optimizations for FPGAs can differ significantly from
optimizations for VLSI. In particular, the FPGA environment constrains the
design space such that only limited parallelism can be effectively exploited to
reduce latency.

Obtaining the right balances between clock
speed, latency, and area in FPGAs can be particularly challenging. The designs
presented here enable a Xilinx Virtex4 FPGA (-11 speed grade) to achieve 270
MHz IEEE compliant double precision floating-point performance with a 9-stage
adder